library ieee;
use ieee.std_logic_1164.all;

entity dFlipFlop is
	port (
		d : in bit;
		clk : in bit;
		clr_al : in bit;
		q, qn : out bit
	);
end entity dFlipFlop;

architecture DATAFLOW of dFlipFlop is

	
	signal p : bit;
	signal q_tmp : bit;
	
begin

	p <= d;
	B1 : block (clk = '1' AND NOT clk'STABLE)
		begin
			q <= guarded p AND clr_al;
			qn <= guarded not p and clr_al;
		end block;

end architecture DATAFLOW;
